|
本帖最后由 Cadence_Hiring 于 2018-6-29 13:09 编辑
Cadence是全球领先的EDA (Electronic Design Automation) 软件开发商以及电子设计自动化解决方案提供商。我们的产品涵盖了电子设计的整个流程,包括系统级设计,功能验证,IC综合及布局布线,模拟、混合信号及射频IC设计,全定制集成电路设计,IC物理验证,PCB设计和硬件仿真建模等。全球知名半导体与电子系统公司均将Cadence软件作为其全球设计的标准
工作地点:北京东城区北三环北京环球贸易中心
主题格式:姓名- 软件研发工程师 Intern-学历-毕业年份
投递邮箱:jianruis@cadence.com
要求:每周工作4天以上,持续至少6个月以上,硕士相关专业2019年及以后毕业
我们给你提供良好的待遇,温馨上进的团队,100%的信任,还等什么,快加入我们!
Position Description:
Develop, enhance and maintain digital mixed signal simulator which supports the co-sim between different HDL languages, such as Verilog, VHDL, SystemVerilog, etc, with some direction from manager or senior engineers
Position Requirements:
1. Familiar with Verilog, VHDL, SystemVerilog language
2. Analog circuit or digital simulator development experiences
3. Skilled in C/C++ programming, familiar with development under Linux/Unix environment.
4. Being familiar with Real number modeling is a plus
5. Being familiar with Digital Mixed-signal design is a plus
6. Being familiar with low power design is a plus
了解更多关于我司的信息,欢迎登陆 Cadence 官网 |
|